| 摘要 |
PURPOSE:To contrive high integration of the titled semiconductor device by a method wherein an element isolation is performed by providing a layer of rhos= 50OMEGA/cm<2> or below, having the same conductive type as the substrate, under the field region which was buried in a semiconductive substrate. CONSTITUTION:A vertical groove 103 is formed in lattice type on the surface (100) of a p type Si substrate 101 by performing a reactive ion etching using a resist 102, B-ions of 1X10<14>/cm<2> is implanted at 50keV, and a p<+> layer 104 is formed by performing heat treatment. The mask 102 is removed, and an SiO2 105 is deposited in the thickness one half or more of the width of the aperture of the groove 103. At this time, the SiO2 is slowly deposited on the substrate 101 and the internal surface of the groove 103 and formed as far as to the aperture part of the groove, thereby allowing almost no rediffusion on the p<+> layer 104. The substrate 101 is exposed by performing an etching on a film 105, a field region 106 is formed, the LSI is isolated by the width 103 of 1mum or thereabout when an n-channel MOSFET is formed as prescribed, a large potential difference is not generated between elements when installation on the package because the layer 104 was formed in rhos=50OMEGA/cm<2>, and high integration of the device can be accomplished without giving an adverse effect on the circuit function. |
