发明名称 CLOCK GENERATING CIRCUIT
摘要 PURPOSE:To simplify one oscillating circuit by using said oscillating circuit as a common oscillation source for the generation of a received sampling clock signal synchronized with a clock run-in signal and the generation of a display clock signal synchronized with a horizontal synchronizing signal. CONSTITUTION:A crystal oscillating circuit 22 oscillates at fixed frequency and one of its outputs is synchronized with a clock run-in signal through a clock run-in signal synchronizing circuit 24. The circuit 24 consists of a counter 42, inverters 43 and 44, NAND circuits 45 and 47, and a shift register 46, and a five-frequency-dividing circuit is reset where the oscillation output signal is put in phase with the clock run-in signal, thereby generating a signal of (8/5)fsc (color subcarrier frequency). The output of the oscillating circuit 22 is supplied to a synchronizing circuit 23 for horizontal synchronizing signal as well. This circuit 23 consists of D-FFs 48 and 49, NAND circuits 50 and 52, and a shift register 51 and in every horizontal scanning period, the five-frequency-dividing circuit is reset to generate a display clock signal of (8/5)fsc. Therefore, only one oscillating circuit is sufficient and all devices can be constitute with digital circuits.
申请公布号 JPS5860886(A) 申请公布日期 1983.04.11
申请号 JP19810158812 申请日期 1981.10.07
申请人 HITACHI SEISAKUSHO KK 发明人 HIRAHATA SHIGERU;OOTA MASUTOMI
分类号 H04N7/083;H04N7/08;H04N7/087;H04N7/088 主分类号 H04N7/083
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