| 摘要 |
PURPOSE:To decide on a locking or unlocking state by laching the output state of a latch circuit, which is set by the output of an OR circuit and reset by a gate delay circuit, by a clock signal. CONSTITUTION:A phase advance and a phase delay signal outputted from a phase comparator 4 are applied to an OR circuit 11. The output signal of the OR circuit 11 is divided into two; one is applied to a gate delay circuit 12, and the other is applied to the set input of a latch 13. The output signal of the gate delay circuit is applied to the reset input of the latch 13. The output signal of the latch 13 is applied to an input D of a D type flip-flop, and the latch clock of a frequency divider 7 is applied to a clock input to latch the state of the data input at a rise of the clock input. The output signal of the D type flip-flop 14 is used for control over other circuits as a signal for showing the decision result of the locking or unlocking state of a PLL. |
