| 摘要 |
PURPOSE:To attain the automatic correction of a logical operation circuit with the comparatively low capacity of hardware by preparating forecasting check bits for the logical operation circuit and comparing the forecasting ckeck bits with that prepared from actual logical operation results. CONSTITUTION:Receiving an output of a logical operation circuit 11 executing AND, OR, EOR, and ADD operation and a bus signal, check bit generating circuits 12a-12f add check bits using Hamming codes to respective input data. Forecasting check bits are prepared through an EOR gate and an OR gate in accordance with said added check bits and the kinds of operation. A circuit 12f compares check bits prepared from the output data of real operation results with forecasting check bits and outputs syndrome patterns S0-S4 for error correction. An error check circuit 13 corrects the output data of the circuit 11 by the syndrome patterns and outputs corrected data. |
