| 摘要 |
An analog to digital conversion circuit of the stage by stage, successive approximation type which incorporates a plurality of cascaded stages. Each stage comprises a mirror current generator for generating first and second mirror currents of the same magnitude as the input current, means for generating a reference current whose magnitude is one half of the full scale current range of the overall conversion circuit, and comparator means connected to the mirror current generator and to the reference current generator for comparing the magnitude of the first mirror current with the magnitude of the reference current and for generating a first binary output signal, as well as a stage output signal which is twice the magnitude of the difference of the first mirror current and the reference current, when the magnitude of the first mirror current is less than the magnitude of the reference current and for generating a second binary output signal as well as a stage output signal having twice the magnitude of the first mirror current, when the magnitude of the first mirror current is less than that of the reference current.
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