| 摘要 |
In a CMOS FATMOS EEPROM, in which a floating gate and its associated tunneling region overlies the source to drain channel, device density is dramatically improved by sharing a source diffusion between adjacent FATMOS transistors and by reversing the function of the source and drain diffusions between reading and writing operations. During writing of a logic "one" into an individual memory cell, the shared diffusion and the control gate are held at +18 volts while the well region is grounded and the other diffusion is selectively grounded.
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