发明名称 LOGICAL CIRCUIT
摘要 PURPOSE:To sufficiently increase the logical amplitude with a single power supply, by connecting the source of a driver FET of a plurality of inverters in cascade connection and in common and floating the source potential from a low potential terminal of a power supply with a diode. CONSTITUTION:Inverters in which normally-on Schottky gate FETsQ21-Q23 are taken as drivers and drains are connected to high potential side via current source load FETsQ24-Q26 are in cascade connection via Schottky diodes D21- D23 for level shift. Sources of the FETsQ21-Q23 are connected in common and the source potential is connected to a Schottky diode D31 to be floated from the ground potential. Since a level shift voltage of each stage is kept constant, FETsQ27-Q29 are connected as a current source with small current value in comparison with the Q24-Q26. The current flowing to the diode D31 is a sum of currents flowing to the Q24-Q26 at all times to be constant, the current acts like a constant voltage, and pinch-off voltage of the FETs is about -0.8V and the logical amplitude is about 1.6V.
申请公布号 JPS5856531(A) 申请公布日期 1983.04.04
申请号 JP19810155175 申请日期 1981.09.30
申请人 TOKYO SHIBAURA DENKI KK 发明人 SHIMIZU SHIYOUICHI
分类号 H03K19/00;H03K19/0952 主分类号 H03K19/00
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