| 摘要 |
PURPOSE:To improve the insulating withstand voltage between the wirings of a planar type field effect transistor of a pectinated structure and a substrate and formed by employing an active layer buried in the surface layer of a semi-insulating arsenic gallium substrate. CONSTITUTION:Numeral 1 designates a semi-insulating arsenic gallium substrate, and 4 an active layer formed by the implantation of n type impurity ions and a heat treatment. A source and drain region 5 formed by the implantation of n type impurity ions and a heat treatment is extended and becomes a wiring n type layer 51. Source and drain electrodes 6, 7 are deposited with gold-germanium or the like, are patterned, are heat treated and are ohmically contacted. The electrodes 6, 7 are extended even on a wiring n type layer 51 and become source and drain wirings 61, 71. A Schottky barrier gate electrode 8 is formed by depositing and patterning aluminum. This gate is also extended and becomes a gate wiring 81. |
