| 摘要 |
A memory (10) can be divided to provide a reduced number of accessible memory elements. By selectively causing an individual address to always assume of predetermined logic state, the number of accessible memory elements is reduced by one half. The selection as to which half is accessible is achieved by applying to an array divider circuit (22) the individual address signal data logic state which corresponds to the predetermined then applying to the array divider circuit (22) an array divider signal. The array divider circuit (22) subsequently provides the individual address signal at the predetermined logic state effectively reducing the number of accessible memory elements by one half. |
