| 摘要 |
<p>An EEPROM (10) which can erase an array (36) of memory cells to all "1"s is capable of causing all of the cells of the array (36) to assume all "0"s, also. The array (36) of memory cells is arranged with one of said memory elements at the intersection of each of a plurality of rows and columns. The memory elements are characterized as assuming relatively high threshold voltage states in response to an erase voltage and relatively low threshold voltage states in response to a program voltage. All columns and rows are selected in order to apply the program voltage to all of the memory elements.</p> |
