发明名称 PUSH-PULL TYPE LOGICAL CIRCUIT
摘要 PURPOSE:To reduce the number of wirings between unit logical gate circuits, in an integrated circuit using a push-pull type logical circuit as the unit logical gate circuit, by inserting a transfer gate to an input stage of the unit logical gate circuit. CONSTITUTION:When a driving MOS transistor (TR)Q1 turns on, e.g. input terminals I1, I2 go to H level and an I3 goes to L level, then an output of an NAND gate G1 goes to H level, a TRT20 of a transfer gate TG1 turns on and a T21 turns off. Thus, a load drive line ld to the inverter gate G1 goes to L level, and the load MOS TRT1 is turned off. When the Q1 is turned off, that is, when all the input terminals I1-I3 of the gate TG1 go to H level, the T20, T21 of the gate TG1 are turned on. Because the impedance of the T22 is large, the signal of H level is applied to the line ld, then a T1 for load of an inverter gate G3 is turned on.
申请公布号 JPS5854733(A) 申请公布日期 1983.03.31
申请号 JP19810151995 申请日期 1981.09.28
申请人 FUJITSU KK 发明人 TAKAHASHI HIROMASA;NISHIUCHI KOUICHI
分类号 H03K19/0944 主分类号 H03K19/0944
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