MICROPROCESSOR WITH MEMORY HAVING INTERLEAVED ADDRESS INPUTS AND INTERLEAVED INSTRUCTION AND DATA OUTPUTS

摘要

A two bus (11, 13), two instruction type, pipelined microprocessor has a control means (45) which orders application of instruction (12) and data (10) addresses to a memory (19) and further interleaves instructions and data on a single bus (13) to achieve maximum efficiency in operation.