| 摘要 |
<p>A multiprocessor computer system wherein memory bus means of separate central processing unit systems are interfaced to an intermemory communication network for transfer of data between memories of said separate central processing unit systems. The intermemory communciation network comprises a plurality of preferably passive intermemory communication links being tapped for connection to link adapters interfacing a number of central processing unit systems to each intermemory communication link. The number of central processing unit system may be different for different intermemory communciation links. The memory bus means are configurated to allow for direct data transfer between any memory fraction of central processing unit systems without interfering with the central processing units that being controlled by direct memory access control means. The multiprocessor computer system includes separate configuration control means being effective to reconfigurate the overall system in the event of failure. The reconfiguration comprises switching of fractions of memory between the memory bus means of at least two central processing unit sytems. Some of said memory fractions being directly addressable by a respective peripheral processor, at least one of said peripheral processors backing up the others for obtaining N+1 redundancy.</p> |
