发明名称 BUFFER STORAGE CONTROLLING SYSTEM
摘要 PURPOSE:To speed up accessing, by providing a comparison circuit which collates a part of content and a part of address information, when the address information performing replacement processing of a part of content comes, while actual write is executed after checking. CONSTITUTION:In reading out the content of a high speed buffer storage device and processing write, when an execution address is set to a register 1, the content of a tag section 2 is read out and when the corresponding address exists, a block number is set to a block number register 5 for actual write processing. When the replacement processing is inserted during this time, the execution address and write address information are compared with a line address comparison circuit 7. When the comparison circuit generates a coincident output, the write processing is done after checking is again performed. Thus, the delay of processing can be avoided.
申请公布号 JPS5853077(A) 申请公布日期 1983.03.29
申请号 JP19810151092 申请日期 1981.09.24
申请人 FUJITSU KK 发明人 TONE HIROSADA
分类号 G06F12/08 主分类号 G06F12/08
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