发明名称 PERIOD CORRECTING CIRCUIT
摘要 <p>PURPOSE:To eliminate a shift of period in case a difference is produced between the clock of a transmitter and the clock of a shaping device for transmission line and a shift is caused in the synchronism of a signal after shaping, by giving a delay to the signal and selecting a proper delayed output when a shift of period is detected with elimination of the noise that is produced from the selection of the delayed output. CONSTITUTION:The signal given from a transmitter undergoes shaping in pulse width and is fed to an input terminal 11 of a correcting circuit 10. A shift register 12 delays the signal of the terminal 11 and has plural delayed outputs Q0,...,Qn. One of these delayed outputs is selected by a multiplexer 13 and delivered. In this case, if a shift of period occurs when the period is shortened, this shift is detected by a deciding circuit 16. Then the multiplexer 13 is controlled to select another output as a delayed output of the register 12. As a result, a spikelike noise is produced, and this noise is eliminated by a spikelike noise signal eliminating circuit 15.</p>
申请公布号 JPS5853219(A) 申请公布日期 1983.03.29
申请号 JP19810152675 申请日期 1981.09.26
申请人 FUJITSU KK 发明人 SAITOU HIROYUKI;AZEGAMI KAZUO;KITANO YUUJI
分类号 H03K5/00;H03K5/04;H04L7/00;H04L25/32;H04L25/40;H04L25/52 主分类号 H03K5/00
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