发明名称 |
Electronic timepiece with frequency correction |
摘要 |
A time correction circuit for an electronic timepiece comprising an oscillator circuit inputting a high frequency standard signal to a divider network, the divider network dividing down the standard signal in a plurality of stages. Correction data is periodically applied to a plurality of divider stages to advance or retard the timing rate when a selected stage achieves a preferred logic state. Occurrence of a logic state in a subsequent divider stage enables the circuits for the next periodic application of the correcting data. Coarse and fine adjustments can be made.
|
申请公布号 |
US4378167(A) |
申请公布日期 |
1983.03.29 |
申请号 |
US19800135028 |
申请日期 |
1980.03.28 |
申请人 |
KABUSHIKI KAISHA SUWA SEIKOSHA |
发明人 |
AIZAWA, HITOMI |
分类号 |
G04G3/02;H03K23/00;(IPC1-7):G04B17/12 |
主分类号 |
G04G3/02 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|