| 摘要 |
<p>PURPOSE:To eliminate the adjustment of a buffer frequency, to eliminate the effect of temperature and to attain circuit integration, by digitizing the circuit with a counter counting clock signals and a preset circuit. CONSTITUTION:When a vertical synchronizing signal (a) is inputted to a preset pulse generating circuit 12, a preset pulse (e) with one clock width synchronized to set an RS flip-flop 11, allowing to set an (n)-bit binary counter 8 via a preset circuit 9 to a preset value. An output pulse C of a count value detecting circuit 10 resets the RS flip-flop 11. While the count value of the binary counter 8 is within a prescribed range, when the signal (a) is inputted, the preset pulse (e) is outputted and the counter 8 is again reset to the preset value and the RS flip-flop 11 is set.</p> |
