| 摘要 |
PURPOSE:To treat all data which are larger than 1 and less than 2 as the data less than 1 in terms of the absolute value in an arithmetic process, by using an adding frequency controlling circuit which controls a holding register of the result of addition. CONSTITUTION:The output of an input register 12 is replaced with the output of a register 17 and added with the output of a holding register 23 of the result of multiplication which holds the product of a coefficient and the delay data to be compensated at a compensating circuit 15 for the result of addition. The corrected value of sum is held at a register 16 and then shifted to the register 17 which holds the result of addition. Both registers 16 and 17 are controlled by an adding frequency controlling circuit 18 and add twice the product of a coefficient RcosW and the delay data to obtain the same result as the sum of a coefficient 2RcosW and the delay data. This result is fed to an output holding register 24 as well as to a delay data register 19 and then multiplied by the coefficient read out of a storage device 20 through a multiplier 22 to be held at a register 23 which holds the result of multiplication. |
