发明名称 EFL Logic arrays
摘要 A logic gate is formed as a full 3-EFL circuit including a full two-level ECL current switch tree and an EFL stage made up of input and output multiemitter transistors. By appropriate connections, the logic gate may be used for a variety of circuits including a 4:1 multiplexer and a comparator of two three-digit binary numbers. The logic gate advantageously is formed in a silicon chip which includes an array of cells each consisting essentially of nine single-emitter transistors, two four-emitter transistors and a number, advantageously nine, of resistors.
申请公布号 US4378508(A) 申请公布日期 1983.03.29
申请号 US19800191394 申请日期 1980.09.29
申请人 BELL TELEPHONE LABORATORIES, INCORPORATED 发明人 SCAVUZZO, ROBERT J.
分类号 H03K19/086;(IPC1-7):H03K17/62;H03K19/08 主分类号 H03K19/086
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