| 摘要 |
PURPOSE:To easily detect failures of a function pattern generator, by constituting a circuit so that a data used actually and a data in which each bit of one address is all 0 can alternately be stored at each one address. CONSTITUTION:An output of an ROM 7 is provided with a logical inverting gate 8 for all 0 detection and an AND gate 9. An AND between a coincidence output A of an AND gate 10 and a failure timing signal (b) is taken at an F/F control gate F110 and directly coupled to a reset terminal of a flip-flop 11. An inverting output of the output A is taken as A', the A' and the (b) are ANDed at an F/F control gate F212 and directly connected to set terminal of the flip-flop 11. Thus, in driving the circuit, the output of the flip-flop 11 changes as 1 0 1 0- and an AC exciting output B is obtained, If a failure takes place, the state of AC oscillation is stopped at the output of the flip-flop 11. |
