发明名称 ERROR CHECK SYSTEM
摘要 PURPOSE:To find a faulty unit circuit easily and accurately by providing an error control flip-flop which inputs the output of a gate circuit added to an error checking circuit for every unit circuit. CONSTITUTION:The output of the error checking circuit 21 in an error check unit A1 is inputted to one input terminal of an AND gate 41. A timing signal T1 is applied to the other input terminal of the AND gate 41, and consequently the output of an error checking circuit 41 is latched by an error holding flip- flop 31. Outputs of respective AND gates 41-4n are inputted to an OR gate 5, whose output is supplied to an error control flip-flop 6. The output of the flip- flop 6 is used as a clock enable control signal for error holding flip-flops 31- 3n.
申请公布号 JPS5851360(A) 申请公布日期 1983.03.26
申请号 JP19810149776 申请日期 1981.09.22
申请人 FUJITSU KK 发明人 ETSUNO MINORU;TATEISHI TERUTAKA
分类号 G06F11/00;G06F11/07;G06F11/34 主分类号 G06F11/00
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