| 摘要 |
1275784 Automatic exchange systems PLESSEY CO Ltd 14 July 1970 [27 Aug 1969] 42670/69 Heading H4K A lock-out circuit (used for example to determine which of a plurality of service demaning speech-path relay sets is to be connected to a register controller) comprises a plurality of stages each including a static switching device which when not disabled, responds to an associated service demand initiating operation of a corresponding slow response output device and inhibiting operation of the static switching devices of subsequent stages, operation of the said output device after its delay inhibiting the response of switching devices in preceding stages. The switching device may be a transistor and the output device a reed relay or slow response electronic equivalent. The circuit functions as a selecting chain selecting on a fixed priority basis between inputs arriving before an output device responds and then functions to lock out any further requests regardless of their priority until the selected requesting unit has been serviced. In one embodiment transistor switches 1TA, 2TA and 3TA each respond when the associated service requests (arriving in random fashion) are present at inputs 1IP, 2IP and 3IP respectively. Any transistor which responds switches to conduction supplying positive potential via diode 1DB, 2DB or 3DB to a conductor 10. By virtue of diodes 1DC, 2DC and 3DC this potential is propergated only to the right switching via resistors such as 2RC and 3RC transistors such as 2TB and 3TB of any stages to the right to conduction, disabling their switching transistors. Thus only the left most of the switching transistors which have operated remains energized for a significant period and energizes an associated output relay 1R, 2R or 3R for a sufficient period to cause it to operate. The energized relay operates an output contact 1R1, 2R1 or 3R1 to effect the desired selection and operates a contact 1R2, 2R2 or 3R2 to supply positive potential via a conductor 11 and diodes such as 1DA, 2DA and resistors 1RB and 2RB to the disabling transistors 1TB, 2TB of preceding stages. A second embodiment using separate feedback paths for each stage and employing OR and inhibit gates in these paths is described. This embodiment (Fig. 1, not shown) includes a plurality of complete lock-out circuits interconnected to form a larger lock-out network in similar fashion. |
