| 摘要 |
PURPOSE:To decrease the signal detecting time through the execution of operation, through by providing a discrete Fourier transformation DFT operation time control circuit, and starting DFT operation section is synchronizing with the reception of signal. CONSTITUTION:A signal from an expander 1 is divided into two and applied to multipliers 2 and 3 of a DFT circuit 30, and an output proportional to the amplitude of signal is generated with adders 4, 5, sample delay circuits 6, 7, square devices 8, 9 and an adder 10. The circuit 30 is provided with a DFT operation time control circuit 40 and a signal from the expander 1 is applied to a limiter circuit 22 of the circuit 40. An output of the circuit 22 is stored at each sampling period in a memory circuit 23, the output of the circuit 23 is applied to a discrimination circuit 24, where the presence/absence of the input to a receiver is discriminated with the output of the circuit 23 and that of an SP output circuit 13 and a control signal is generated. A delay circuit 25 instructs the start of operation section in synchronizing with the reception of signal to the circuit 30, the result of operation from the adder 10 is applied to a memory 21 with the output of a delay circuit 28 to decrease the signal detection time. |
