| 摘要 |
<p>PURPOSE:To improve a data transfer rate, by managing the data transfer request, which is transmitted from an optional linkage device, with a cyclic stage and advancing the stage to the next linkage device when the linkage device has not the transmission request on the stage assigned to its own system. CONSTITUTION:Timings of the start of data transfer in linkage devices connected to a parallel bus gate 24 of the parallel bus management system are determined by a commonly managed cyclic stage. A counter 20 which transmits a start pulse to this circuit, an SYN code adding circuit 21, a stage counter 22, an SYN detecting circuit 23, etc. are provided. Further, flip flops 26-31, a buffer register 32, an address coincidence detector 33, etc. are provided. When the linkage device has not the transmission request in its own system, the synchronizing bus is divided logically, and the stage is advanced to the next linkage device. When it has the transmission request in its own system, the private timing is passed to the stage managed by its own system, the request is issued to the parallel bus, and the stage is advanced to the next linkage device when the data transfer service is terminated, and thus, the data transfer rate is improved.</p> |
