发明名称 Multilevel logic circuit.
摘要 <p>A Multi-Level Logic Circuit is described, with the hardware of the circuit capable of being constructed to operate in a chosen base. The circuit includes at least: (a) One input level detector which can receive one or more multi-level inputs, (b) Control switching means, and (c) An output level generator delivering a single multi-level output.</p><p>Various logic gates operating in any base can be derived from the generalized circuit of this invention. Basic multi-level logic gates include a (n - 1) complementer, where an output of (n - 1 - a) is generated from a discrete input "a" where n is the base for which the circuit is constructed. A complementary maximum gate is also described in which the circuit provides the (n - 1) complement of the highest logic level detected on input lines to the input level detector. Various other multi-level logic circuits can be constructed by combining the multi-level complementer, and multi-level complementary maximum gates. Circuits are also described where there are more than one input level detector or control switching means to provide binary operations on inputs to the multi-level logic circuits, e.g. addition, multiplication, in any desired base. Circuits are illustrated, constructed to operate in base 10.</p><p>The multi-level logic circuit is similar to a binary circuit in that it operates on discrete logic levels. It is not an analog circuit.</p>
申请公布号 EP0074722(A2) 申请公布日期 1983.03.23
申请号 EP19820304327 申请日期 1982.08.17
申请人 DEVELOPMENT FINANCE CORPORATION OF NEW ZEALAND 发明人 SENGCHANH, CHANTY
分类号 H03K19/20;G06N7/04;H03K19/082;(IPC1-7):03K19/00 主分类号 H03K19/20
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