发明名称 MOS TYPE INTEGRATED CIRCUIT DEVICE
摘要 PURPOSE:To easily and accurately shake off the latent defective chips in an extremely short time for the titled device by a method wherein a high voltage is enabled to be applied in a screening process by providing a pad exclusively used for a capacitor part without a diffusion layer or with a diffusion layer which is far deeper than the peripheral circuit. CONSTITUTION:The polycrystalline silicon pieces 211, 212...21N, 211', 212'...21N' on the capacitor part of a memory cell are interconnected by Al wirings 22 and 22', and these silicon pieces are also connected to the bonding pad 23 for capacitor of the memory cell which supplies a constant voltage (VDD, VSS and the like). On the other hand, a bonding pad 24 is used to supply the same voltage to the diffusion layers 251 and 252 of the peripheral circuits such as a transistor and the like. To be more precise, the same power source terminal is used for both the bonding pad 23 to be used for the capacitor of the memory cell and the bonding pad for the peripheral circuits other than said bonding pad 23, and the number of the pad is increased by one when compared with the device which was heretofore in use.
申请公布号 JPS5848449(A) 申请公布日期 1983.03.22
申请号 JP19810146532 申请日期 1981.09.17
申请人 TOKYO SHIBAURA DENKI KK 发明人 KINOSHITA HIROYUKI
分类号 G11C11/401;G11C29/00;G11C29/06;H01L21/60;H01L21/822;H01L21/8242;H01L23/528;H01L27/04;H01L27/10;H01L27/108;H01L29/94 主分类号 G11C11/401
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