| 摘要 |
PURPOSE:To perform high-speed processing while respective partial functions overlap each other in parallel, by estimating a feedback signal when a result to be fed back should not have delay, and using said estimated value. CONSTITUTION:In a block U1, arithmetic regarding a part other than the phase angle of a sampled-value operation type detection carrier is carried out. An automatic phase control circuit (APC) in a block U3 calculates a tandem lag filter output and performs arithmetic according to the estimation equation of the phase angle of the detection carrier by using the calculated filter output. In a block U2, an automatic timing control circuit (ATC) extracts timing information from a detection signal, and a circuit SE finds an error of the detection signal to be used for automatic equalization and its estimated value. In this constitution, a feedback loop is formed on the blocks U2, U1, U3, and U2 in order. |
