发明名称 GATE SIGNAL GENERATING CIRCUIT FOR GATE TURNOFF THYRISTOR
摘要 PURPOSE:To prevent the breaking of GTO and the incomplete ignition of the titled circuit by a method wherein an ON signal and a delay signal are generated in synchronization with the ignition signal in accordance with a switching signal, and a device with which the switching and delay signals will be interlocked is provided. CONSTITUTION:A gate signal generaing circuit, with which On and OFF positions will be given to the multiple series-connected GTO by switching signals T1 and T2, is provided. Then, ON signals N1 and N2 are generated in the gate signal generating circuit in synchronization with ignition signals ON1 and ON2 in accordance with switching signals T1 and T2. Said switching signals T1 and T2 and delay signals D1 and D2 are interlocked each other. Thus, the entire emitter region of the GTO can be ignited by adding the ON signals N1 and N2 in the minimum required time interval and, at the same time, as the preparations for the ignition signals ON1 and ON2 are completed, the breakage of GTO due to shortages of dv/dt, an off-pulse current, an on-pulse current or the like can be prevented.
申请公布号 JPS5846864(A) 申请公布日期 1983.03.18
申请号 JP19810141973 申请日期 1981.09.09
申请人 TOKYO SHIBAURA DENKI KK 发明人 HOSOKAWA YORIO;FUKAZAWA KATSUMI
分类号 H02M1/06;H03K17/10;H03K17/73 主分类号 H02M1/06
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