| 摘要 |
<p>1,246,592. Arithmetic circuits. INTERNATIONAL BUSINESS MACHINES CORP. 15 April, 1970 [25 April, 19691, No. 17934/70. Heading G4A. Arithmetic apparatus with parallel input obtains digits of the reciprocal of an input number by combining the input digits and products of them obtained by logic gating means, or (claimed separately) obtains digits of a quotient each as a sum of products of a dividend digit with a factor, factors being obtained recursively as sums of products from the divisor digits and factors. In a first embodiment, the reciprocal of a first parallel binary number (which may be a divisor) is obtained based on expressing each binary order of the reciprocal in terms of the difference of two sums of digits and products of digits of the input number. Combinatorial logic using AND gates produces the products (since the product of two or more bits is their AND). Two trees of carry-save adders and half-adders receive the digits and products of digits for the two sums respectively (in all orders), the tree outputs being subtracted by complemented addition to provide the reciprocal. The reciprocal can be multiplied in a parallel binary multiplier by a dividend to obtain a quotient. The quotient is then justified to take account of initial left-justification of dividend and divisor. In a second embodiment, a serial-parallel network of adder and multiplier units obtains factors of the form: from inputs - D n where D n is a typical binary digit of a parallel divisor and P 0 = 1. A second serial-parallel network of adder and multiplier units combines these factors P n with the binary digits N n of a parallel dividend to obtain quotient digits q n according to: The adder units may be implemented as trees of carry-save adders.</p> |
