| 摘要 |
PURPOSE:To attain a high-speed arithmetic process for a parallel processor system, by having a control so that just a single processor is set under the transmission mode with other pricessors all set under the reception mode. CONSTITUTION:A control arithmetic controller 102 monopolizes a common bus 101 to transfer the data among processors after the arithmetic execution phase and at the same time sets the processors 103-106 under the reception mode by the monopolizing signal. Then a switch control signal is fed to the processor 103 via a signal line 107 for the switching to the transmission mode. Thus the processor 103 is set under the transmission mode. The processor 103 feeds the data of a number indicated previously to the processors and then switches its own working mode into the reception mode. Then the control signal is fed to the processor 104 via a signal line 108 in order to set the processor 103 under the transmission mode. In such way, the transfer of data is carried out among n-units of processors, and the processor 102 is switched to the arithmetic execution phase when the switch signal to the transmission mode arrives at the processor 102. |
