| 摘要 |
PURPOSE:To eliminate a high-speed operation of a logic tester, by actuating a microprocessor with each instruction and making sure of the test working result. CONSTITUTION:A test control signal TCT is produced from a logic tester LGT, and the output D of an interface circuit 4 is set at a high level by a degree equivalent to a clock. Then a halt terminal HALT' of a microprocessor MPU5 is set at a high level. As a result, the MPU5 fetches the test data given from an ROM1 to the data buses D0-D7 and executes it. Based on the result of execution, the MPU5 transmits the address data and the instruction execution data through terminals A0-A15 and the buses D0-D7 and at the same time transmits the signal through a valid memory address terminal VMA. The circuit 4 fetches the signal and clock phi2' and feeds the output of AND46 to an address latching circuit 2 and a data latching circuit 3. The tester LGT fetches the data from the terminals TA0-15 and TD0-8 respectively to perform a test of confirmation for the working of the MPU5. |
