发明名称 FRAME SYNCHRONIZING CIRCUIT
摘要 PURPOSE:To reduce generation probability of an erroneous synchronization by using plural cascade-connected time filters inputting a synchronizing pattern bed from a correlation detector. CONSTITUTION:A correlation detector 2 receives a receiving data train 101 and a clock signal 102, detects a synchronizing pattern from the receiving data train, and inputs it to a time filter 10. The time filters 10-12 are cascade-connected, and a clock signal of 1 frame length counted by a frame counter 1 is inputted to the filters 10-12 in order. An output of the counter 1 is inputted to a decoder 3, the decoder 3 decodes its contents and generates a frame pulse 106, and applies it to a control signal generating circuit 13. In case when a control signal 203 to the filters 10-12 from the circuit 13 is ''write'', the filters 10-12 store contents of the counter 1 in order in a memory whenever a pulse comes into an input. In case when the signal 203 is ''read-out'', the filter 10 generates a forecasting pulse whenever the contents of the counter 1 coincide with the stored contents, outputs only a pulse whose time has coincided with the forecasting pulse in the input pulse, and generation of an erroneous synchronization is reduced.
申请公布号 JPS5843647(A) 申请公布日期 1983.03.14
申请号 JP19810141664 申请日期 1981.09.10
申请人 NIPPON DENKI KK 发明人 ICHIYOSHI OSAMU
分类号 H04J3/06;H04L7/08 主分类号 H04J3/06
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