发明名称 LOGICAL CIRCUIT
摘要 PURPOSE:To obtain output voltage of a high level for driving a large current, by connecting in series p-channel and n-channel MOSFETs whose gates have been connected in common, and connecting an npn transistor in parallel with the p- channel MOSFET. CONSTITUTION:Between an electric power supply terminal 11 and a ground terminal 12, a p-channel CHMOSFET transistor TR13 and an NCHMOSFET TR14 whose mutual gates have been connected to each other are connected in series. An npn TR15 is connected in parallel with the TR13, the collector and the emitter of the TR15 are connected to an electric power source VDD, and a connecting point of the TRs 13, 14, respectively, and to the base of the TR15, an input signal is connected through an inverting circuit 17 so as to execute a switching operation opposite to the TR14. In case when an output current of this circuit is small, a CMOS circuit constituted of the TRs 13, 14 is operated, a high-level output voltage characteristic is obtained as shown by (a) in the figure, and when the output voltage drops by 0.4V or so, a circuit constituted of the TRs 15, 14 is operated, and a large-output current characteristic is obtained as shown by (b).
申请公布号 JPS5843627(A) 申请公布日期 1983.03.14
申请号 JP19810142102 申请日期 1981.09.09
申请人 TOKYO SHIBAURA DENKI KK 发明人 SATOU KOUICHIROU
分类号 H03K19/01;H03K19/017 主分类号 H03K19/01
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