发明名称 LOCKING PULSE GENERATING DEVICE
摘要 PURPOSE:To generate a locking pulse whose geneating period is not overlapped on each other, by a small number of gate circuits, by providing 3 RS-FF circuits 3, coincidence gates for setting or resetting these FF circuits in order, and a distributing circuit. CONSTITUTION:A titled device is provided with the first-third RS-FF circuits 100-300, an NAND gate 6 to which an output signal of the circuit 100, the first clock pulse, and the second clock pulse of frequency of 1/2 of the first clock pulse are provided, and NAND gate 9 to which an output signal of the circuit 200 and said 2 clock pulses are provided, an NAND gate 12 to which an output signal of the circuit 300 and said 2 clock pulses are provided, and a distributing circuit for generating the locking pulses of 2 systems whose generating period is not overlapped on each other, from output signals of the circuit 200 and 300, and sending them out to output terminals Z1, Z2. In this way, it is possible to generate a locking pulse whose generating period is not overlapped on each other, by a small number of gate circuits.
申请公布号 JPS5843618(A) 申请公布日期 1983.03.14
申请号 JP19810142723 申请日期 1981.09.09
申请人 MATSUSHITA DENKI SANGYO KK 发明人 MIZUGUCHI HIROSHI
分类号 H03K5/1532;H03K5/15;H04L7/02 主分类号 H03K5/1532
代理机构 代理人
主权项
地址