| 摘要 |
PURPOSE:To decrease the waiting time of the priority data and to attain the pre-transmission of the priority data without lowering the using efficiency of a circuit, by delivering consecutively plural priority data to the circuit and delivering only a non-priority data to the circuit at one time respectively. CONSTITUTION:The 1st and 2nd memory means 71 and 72 store the priority data having a high degree of priority and the non-priority data having a low degree of priority respectively. The 3rd memory device 76 stores the data which is fed to the circuit. The priority data stored in the memory 71 are fed consecutively to the memory 76 until they reach a prescribed number; while only one of the non-priority data stored in the memory 72 is fed to the memory 76 when the prescribed conditions are satisfied. As a result, the priority data can be fed to the circuit with the minimum waiting time without lowering the circuit using efficiency regardless of a high speed of transmission. |
