发明名称 DIGITAL PHASE LOCKING CIRCUIT
摘要 PURPOSE:To realize acquistion at a high speed and to reduce jitters caused after the acquistion, by varying the number of stages of a random walk filter contained in a phase locked loop and adding a random walk filter which controls the above-mentioned number of stages. CONSTITUTION:A random walk filter 2A has the up-random, stay random and down-random walk actions in response to the plus, zero and minus of the output P(n) of a phase detector 1. If the result of this walk action is equal to the stage number N(n) of a time point (n), phase advancing information is fed to a VCO3. Phase delaying information is fed if the result is equal to the stage number -N(n). Otherwise the state maintenance information is fed, respectively. The VCO3 changes the phase of the output signal by the information Q1(n). A control random walk filter 2B performs a random walk action by the information Q1(n). If the result of this walk action is equal to the stage number N2 and -N2, the information indicating a reduction of the stage number N(n) of the filter 2A is fed. Otherwise the information indicating the maintenance of the stage number is fed.
申请公布号 JPS5840932(A) 申请公布日期 1983.03.10
申请号 JP19810137747 申请日期 1981.09.03
申请人 HITACHI SEISAKUSHO KK 发明人 SHINADA SHIGEO
分类号 H03L7/06;H03L7/08;H03L7/107 主分类号 H03L7/06
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