| 摘要 |
PURPOSE:To prevent latch-up, and to fine the device by positioning an insulating layer at one side of an adjacent p layer or n layer isolated by the insulating layer and one part or all of the interface of a substrate while forming a p<+> layer under an isolation layer. CONSTITUTION:A resist mask 103 is shaped, the p<+> layers 104 are formed through ion implantation, Al 105 is stacked, and the isolation layers 106 are shaped through etching of SiO2 102 by masks 1052. The surface of the substrate is coated selectively with SiO2 108, poly Si 109 is stacked, the p layer 110 is molded by diffusion from the substrate through the irradiation of laser beams, and Si3N4 111 is deposited. The p layer 110 is etched through reactive ion etching while using Si3N4 111' remaining in a concave section as a mask, and the n layer 113 is shaped through the selective implantation of ions. When the CMOS device is manufactured according to a predetermined method, the complementary transistor is insulated by the films 106, a parasitic transistor is not formed, the device is not latched up, the surface of the element is flat, the degree of integration can be increased, and characteristics are also excellent. |
