发明名称 COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE AND ITS MANUFACTURE
摘要 PURPOSE:To prevent latch-up, and to fine the device by positioning an insulating layer at one side of an adjacent p or n layer isolated by the insulating layer and one part or all of the interface of a substrate. CONSTITUTION:SiO2 105 is formed selectively onto the p type Si substrate 101, the surface of the substrate is coated selectively with SiO2 107, and poly Si 108 is deposited. A p layer 109 is manufactured by diffusion from the substrate through the irradiation of laser beams, and plasma Si3N4 110 is stacked. The p layer 109 is etched through reactive ion etching while using Si3N4 110' remaining in a concave section as a mask, and the p layer 111 and the n layer 112, which are isolated, are shaped through the selective injection of P ions. The complementary MOS device is formed according to a predetermined method. According to this constitution, the complementary transistor is insulated by the SiO2 film 107, a parasitic transistor is not shaped, and the device is not latched up. The regions 111, 112 are flattened, the region 112 is determined by the width of the isolation layer 105, lateral diffusion is obstructed, and the device having high density is obtained.
申请公布号 JPS5840851(A) 申请公布日期 1983.03.09
申请号 JP19810138831 申请日期 1981.09.03
申请人 TOKYO SHIBAURA DENKI KK 发明人 MAEDA SATORU;IWAI HIROSHI
分类号 H01L27/08;H01L21/20;H01L21/762;H01L21/8238;H01L27/092;H01L29/06;H01L29/78 主分类号 H01L27/08
代理机构 代理人
主权项
地址