| 摘要 |
PURPOSE:To control memory access timing externally and optionally by inputting timing information from outside of a circuit module, and forming the memory access timing signal on the basis of the input information. CONSTITUTION:When a bus confirmation signal 36 is turned on by a processor 31, a timing information signal 37 generated by a timing generating circuit 34 is inputted to a timing generation part 35 in a circuit module 30. On the basis of this input signal 37, the generation part 35 outputs an address strobe 38, a data strobe 39, an address output timing signal 40, a data output timing signal 41, and a data latch timing signal 42. A memory control circuit 33 uses the strobes 38 and 39 to generate an access signal 43 for a memory 32. Consequently, memory access timing is controlled externally and optionally, and memory access matched with the memory speed is made possible for a memory with any speed. |
