发明名称 DATA SYNTHESIZING PROCESSION SYSTEM
摘要 PURPOSE:To synthesize fixed-form data and variable data into one in making no conscious of the difference in the form to a program, by simultaneously read out memory blocks of the fixed-form data and variable data allotted to the same address area. CONSTITUTION:The software of a CPU1 reads a necessary number of fixed-form patterns out of a file, and then transfers them to a communication controller 2, which stores them in a permanent data memory 9. For outputting synthesized data to some terminal, the software of the CPU1 transfers variable data to the controller 2, which is started. According to the order in the transferred data, the controller 2 writes the data in a variable data memory 10 which corresponds to a prescribed circuit number. Once the writing of the variable data ends, a microprocessor unit 16 performs logical-to-physical address conversion to read out data out of the memories 9 and 10, and then writes them in line buffers 20 and 21 of a corresponding line adapter 15.
申请公布号 JPS5839366(A) 申请公布日期 1983.03.08
申请号 JP19810136701 申请日期 1981.08.31
申请人 FUJITSU KK 发明人 NAKAYAMA TAKESHI;KIMURA TATSUO;NAKAGAWA KOUYOU
分类号 G06F17/21;G06Q10/10;G06T11/60 主分类号 G06F17/21
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