| 摘要 |
PURPOSE:To make pulse widths of the input and the output approximately equal to each other, by delaying the signal, which is applied to the control terminal of a tri-state logic circuit, more than the signal applied to an input terminal. CONSTITUTION:An input signal (a) is applied to the input terminal of a tri-state logic circuit A through an inverter E. The input signal is applied to the control terminal of the logic circuit A through inverters E and F. That is, the input signal is applied to the control terminal after a delay longer than that for the input signal applied to the input terminal. Consequently, the leading edge of the output of the logic circuit A is determined by the signal of the control terminal, and the trailing edge is determined by the signal of the input terminal, and thus, an output (e) of an inverter B is approximately equal to the pulse width of the input signal. |
