| 摘要 |
A system for forming address signals which address respective converter switches in a frequency converter. The frequency converter is of the type wherein a DC voltage is provided for supplying electrical energy to phase outputs thereof in response to the states of the converter switches. In accordance with the invention, the phase output voltages, phase output currents, and predetermined desired phase currents are treated as space vectors from which are generated control difference space vectors. In one embodiment, a trigger pulse is generated externally and may be suppressed when the control difference vector has a value which is below a preselected tolerance limit. In a further embodiment, the trigger pulse is generated internally and is suppressed if the tolerance limit is exceeded. Upon the occurrence of each trigger pulse, a voltage space vector is addressed having a direction which is opposite to the control difference space vector. Such an oppositely directed space vector produces a fast reduction of the control difference. In a preferred embodiment, the discrete voltage space vectors are selected in accordance with the sign of the control difference. Thus, the particular space vector which is closest to the vectorial difference between the desired and actual load current vectors is selected. In further embodiments, the addressing signals may be formed so as to cause the phase outputs of the frequency converter to short circuit at a selectable one of the DC input terminals thereof. |
