发明名称 HARDWARE CONTROLLING SYSTEM FOR PROCESSOR
摘要 PURPOSE:To decrease the length of a microinstruction and the number of steps, by controlling a control item which can be performed by giving a prescribed control to the hardware depending on characteristics of an instruction read out from a main storage device, with an auxiliary control code. CONSTITUTION:An instruction read out from a main storage device is stored in an instruction register 1 and the content of a conversion memory 3 is read out by taking an instruction code 2 in the instruction register 1 as an address. A part of the read-out content is a microinstruction address 7 and the rest is an auxiliary control code 8 and stored in an auxiliary control register 9. The hardware controls the operation depending on the content of the register 9. The code 8 stored in the register 9 remains unchanged independently of the revision of a micro program counter 6, until a new instruction is read out to the register 1 from the main storage device.
申请公布号 JPS5837744(A) 申请公布日期 1983.03.05
申请号 JP19810134064 申请日期 1981.08.28
申请人 HITACHI SEISAKUSHO KK 发明人 YAMAMOTO NOBORU
分类号 G06F9/22;(IPC1-7):06F9/22 主分类号 G06F9/22
代理机构 代理人
主权项
地址