| 摘要 |
PURPOSE:To eliminate disadvantages of series and parallel operating systems respectively, by providing a Y register group arranged with n-set of m-bit registers in parallel and an S register group with the similar constitution. CONSTITUTION:A YM1 register 22 and an SM1 register 25 are connected to an adder 28 via connecting lines 29 and 32. The content of the YM1 register 22 and of the SM1 register 25 is summed at an adder 28, and the result of addition is stored in the register 25 via a connecting line 35. Similarly, the operation of YM2+SM2,-, YMn+SMn is executed in parallel. Taking a time required for the addition of one-bit as DELTAt', the time required for m-sets of integrating operation for n-bit with this constitution is mXDELTAt', and the operation time can be decreased to 1/n in comparison with a series operation. |
