| 摘要 |
PURPOSE:To prevent collision of data on a bus line, by performing the control for data write and readout in an RAM through use of a CPU. CONSTITUTION:In performing the control of data write and readout in an RAM 2 having a bidirectional bus with a CPU, a bidirectional bus gate 4 is provided for a data line and the data line is split into two (data 1 and 2), and the control of a chip selection CS in the bus gate 4 is performed with a control circuit consisting of inverters INV1,INV2, flip-flops FF1,FF2, an NAND gate G1, an AND gate G2, and an OR gate G3. |
