| 摘要 |
The phase locked loop serves to synchronise input signals (E) with reference signals (B) which are obtained from clock pulses (TA) with a variable repetition frequency which are generated in a clock generator (TG). The input signals (E) and the clock pulses (TA) are fed, with the intermediate connection of frequency dividers (Z1, Z2), to a phase detector (PD) which generates control signals (ST) via a filter (F) for the clock generator (TG) with which the repetition frequency of the clock pulses (TA) is modified. A switching stage (SS) disposed between the frequency dividers (Z1, Z2) and the phase detector (PD) ensures reliable phase-locking of the loop even when the repetition frequency of the clock pulses (TA) exceeds an upper limit. The switching stage (SS) checks the pulse period of signals allocated to the input signals (E) and extends them to a pre-defined value if required. <IMAGE>
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