发明名称 MULTIPLIER
摘要 PURPOSE:To improve the throughput of an array system multiplier by successively executing multiplication basing on parallel operation system like a pipe line system. CONSTITUTION:A prestage operating circuit K is formed by half address 1-3 and full address 4-9 , a ripple charrying type counting circuit E is formed by full adders 10-12 and the prestage operating circuit K and the ripple carrying type counting circuit E are connected through a 10-bit register 13 for temporally storing the operation results of the operating circuit K. Consequently the operations of the operating circuit K and the ripple carrying type counting circuit E are operated simultaneously and the product data D1-D8 of multiplied results are stored in a register 14.
申请公布号 JPS5831449(A) 申请公布日期 1983.02.24
申请号 JP19810128720 申请日期 1981.08.19
申请人 TOKYO SHIBAURA DENKI KK 发明人 NODA MAKOTO
分类号 G06F7/53;G06F7/52;G06F7/527 主分类号 G06F7/53
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