DIGITAL SWITCHING NETWORK

摘要

The input connections (32LE) are shared between four amplifying input circuits (CAE1-4) containing amplifiers (AF) and synchronising units (SYN). Each amplifier circuit is connected to a buffer memory (CMT1-4) containing input control circuits (CE) and serial to parallel data converters (CSP). An access circuit (CA) allows access to the buffer memory (MT). A counter (CR) provides downstream control of the addressing while memory read is enabled by a control circuit (CMC) driven by the marker (MQ) containing a microprocessor (mpc). The microprocessor is connected via duplexed point to point connections (RIT) using access units (AR1,2). A clock unit (MD) provides the necessary clock signals from an oscillator circuit. The memory contents are output via an output amplifier circuit (CAS) containing a buffer register (R) and parallel to serial data converter (CPS) which serves a group of output amplifiers (AS).