DATA PROCESSING SYSTEM HAVING SYNCHRONOUS BUS WAIT/RETRY CYCLE

摘要

A data processing system which includes a central processing unit coupled over a common bus with a plurality of input/output controllers (IOCs) and main memory includes apparatus which allows an IOC to signal the CPU to wait and retry the current I/O instruction. Other apparatus is provided which enables the CPU to continually retry the I/O instruction until the IOC accepts or rejects the I/O instruction and which further allows the CPU to suspend the retrying of the I/O instruction, to process interrupt requests and data transfer requests from any one of the plurality of IOCs. After processing the interrupt or data transfer request, system control is returned to retrying the I/O instruction.