| 摘要 |
PURPOSE:To improve linearity of a pulse width modulating output, by counting an output of a means for gating a clock pulse in accordance with a control signal, and controlling an output of a counting value detector by a preset pulse. CONSTITUTION:A data value of a digital modulating signal di is detected by a detector 4, whether it is a prescribed data value or not is detected, and a signal (f) of H or L is outputted to an output generator 6. The signal di and a preset pulse (e) from a pulse generating circuit 7 are inputted to a presetting circuit 2, an FF of a binary counter 1 is set or reset, and an output from a clock gate 5 is counted. Subsequently, when the counting value becomes a prescribed value, the clock gate 5 is opened by an output (b) of a counting value detector 3. After that, when the output (b) is applied, a pulse width modulating output (h) is obtained from the output generator 6. In this case, in order to eliminate influence of a delay time of the output (b), the output (h) is controlled at the time point when the preset pulse (e) has been generated. |
